Udemy - Simple Axi Bus Design Using Verilog Hdl

Files:

• Get Bonus Downloads Here.url (0.2 KB)
~Get Your Files Here ! 1 - Course Introduction
• 1 - Introduction.mp4 (22.5 MB)
• 2 - AMBA introduction.mp4 (6.3 MB)
• 3 - Comparision between AHB AXI APB.mp4 (12.9 MB)
2 - AXI bus
• 10 - Read process Timing diagram.mp4 (15.1 MB)
• 11 - Dependencies between channel handshake signals.mp4 (10.9 MB)
• 4 - Introduction to AXI.mp4 (6.1 MB)
• 5 - AXI channel Architecture of Readwrites.mp4 (17.6 MB)
• 6 - AXI signals.mp4 (12.0 MB)
• 7 - Handshaking signals.mp4 (12.0 MB)
• 8 - Signal Diagram.mp4 (20.0 MB)
• 9 - Write process Timing diagram.mp4 (12.1 MB)
3 - Implementation of Simple AXI bus
• 12 - AXI state machine for write read.mp4 (2.4 MB)
• 13 - AXI MasterSlave Block diagram and Writeread process.mp4 (11.1 MB)
4 - Source code
• 14 - Design of AXI bus using verilog HDL write process.mp4 (279.4 MB)
• 14 - axi-master-write.v (3.1 KB)
• 14 - axi-slave-write.v (2.7 KB)
• 15 - Design of AXI bus using verilog HDL Read process.mp4 (123.3 MB)
• 15 - axi-master-read.v (2.5 KB)
• 15 - axi-slave-read.v (2.2 KB)
• 16 - AXI master slave.mp4 (12.8 MB)
• 16 - axi-master.v (1.6 KB)
• 16 - axi-slave.v (1.5 KB)
• 17 - Test bench simulation.mp4 (19.0 MB)
• 17 - design.sv (0.2 KB)
• 17 - testbench.sv (2.3 KB)
• Bonus Resources.txt (0.4 KB)